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ISL29033
Electrical Specifications
unless otherwise specified. (Continued)
V DD = 3.0V, T A = +25°C, R EXT = 1M Ω 1% tolerance, 16-bit ADC operation,
MIN
MAX
PARAMETER
DESCRIPTION
CONDITION
(Note 6)
TYP
(Note 6)
UNIT
V IL
V IH
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
1.25
0.55
V
V
I SDA
I INT
SDA Current Sinking Capability
INT Current Sinking Capability
V OL = 0.4V
V OL = 0.4V
4
4
5
5
mA
mA
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. A 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count as a fluorescent light with
illuminance at the stated lux.
8. An 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count as solar light with
illuminance at the stated lux.
I 2 C Electrical Specifications
and 1M ? 1% tolerance.
For SCL and SDA (Figure 2), unless otherwise noted, V DD = 3V, T A = +25°C, R EXT = 499k ? 1%
MIN
MAX
PARAMETER
V I2C
DESCRIPTION
Supply Voltage Range for I 2 C Interface
CONDITION
(Note 6)
1.7
TYP
(Note 6)
3.63
UNIT
V
f SCL
V IL
V IH
V hys
V OL
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level Output Voltage (Open-drain) at 4mA Sink
Current
1.25
0.05V DD
400
0.55
0.4
kHz
V
V
V
V
I i
t SP
t AA
C i
Input Leakage for each SDA, SCL Pin
Pulse Width of Spikes that must be Suppressed by
the Input Filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL Pin
-10
10
50
900
10
μA
ns
ns
pF
t HD:STA
t LOW
t HIGH
t SU:STA
t HD:DAT
t SU:DAT
t R
t F
t SU:STO
t BUF
C b
R pull-up
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Capacitive Load for Each Bus Line
SDA and SCL System Bus Pull-up Resistor
After this period, the first clock pulse
is generated.
Measured at the 30% of V DD crossing
(Note 9)
(Note 9)
Maximum is determined by t R and t F
600
1300
600
600
30
100
20 +
0.1xC b
20 +
0.1xC b
600
1300
1
400
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
k ?
5
FN7656.2
February 25, 2013
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